You could also try clocking logic on the falling edge and the rising edge. You can put a 12 MHz crystal on your PCB to minimize emissions, and then inside the FPGA you can multiply the clock up to e.g. Xilinx has called them DCM (Digital Clock Managers) in the past, although I think Spartan 6 has an actual PLL and DCM-like blocks (may be called something else these days). ![]() Most FPGAs (including your Spartan 6) have dedicated logic for generating different clocks from a source clock. ![]() What are generic approaches to process such signals? If external signals are coming with higher frequency then clockįrequency (or if processing of a signal takes multiple clock cycles),
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